Many CMOS integrated circuits utilize a substrate with twin tubs. One tub is typically doped with an n-type dopant, while the other tub is doped with a p-type dopant. An example of a twin tub patent is found in U.S. Pat. No. 4,435,896, issued to Parillo et al.
An artifact of some twin tub manufacturing processes is a height difference between the upper silicon surface of n tub and the p tub. In other words, the silicon surface of the p tub is not co-planar with the silicon surface of the n tub. This lack of co-planarity may contribute to difficulties in achieving proper stepper focus as integrated circuitry dimensions shrink. (Subsequent attempts to remove or reduce the lack of co-planarity may require extra masks and incur extra costs.)
Those concerned with the development of integrated circuits have consistently sought new and improved methods for forming twin tubs within a semiconductor substrate.